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ZEN2002AP
P ROGRAMMABLE UNIVE RSAL COUNTE R
Description ZENIC INC. ZEN2002AP is a 24 bit pr ogr a m m a ble u n iver sa l cou n t er LSI . TH E ZEN2002AP cou n t s ph a se-sh ift ed sign a ls a n d u p/down pu lse sign a ls, gen er a t ed fr om r ot a r y en coder s or lin ea r sca les. Sin ce t h e cou n t er r espon se speed is a s h igh a s 20MH z(MAX),t h e ZEN2002AP is u sed in a va r iet y of h igh speed ser vices in clu din g digit a l ser vo con t r ol a n d pr ecision m ea su r em en t . TH E ZEN2002AP is pr ovided wit h a fu n ct ion wh ich m on it or s t h e in pu t sign a ls a n d det ect s a n y a bn or m a l in pu t a ccom pa n ied wit h n oise or ot h er dist u r ba n ces, so t h a t t h e r elia bilit y of cou n t ed va lu es a r e secu r ed.
1, Features 24 bit bin a r y u p/down cou n t er . Cou n t er r espon se speed: 20MH z.(MAX.) ( CLK f0 = 20MH z a t 50% du t y) In pu t fr equ en cy of cou n t pu lse. P h a se-sh ift ed sign a l in pu t : A/B ph a se in pu t DC ~ 5MH z. (less t h a n f0 ~ 1/4) U p/down pu lse sign a l in pu t : U p/down in pu t DC ~ 10MH z (less t h a n f0 ~ 1/2) CLK fr equ en cy DC ~ 20MH z. (MAX.: du t y r a t io 50%) Dir ect ion r ecogn it ion for u p/down cou n t in g. Abn or m a l in pu t det ect ion cir cu it . P r eloa d r egist er for t h e u p/down cou n t er . La t ch r egist er for t h e u p/down cou n t er . Refer en ce va lu e - cou n t va lu e coin ciden ce det ect ion fu n ct ion . Mom en t a r y ou t pu t : TTL In t er r u pt ou t pu t (la t ch ed) : open collect or On -ch ip st a t u s r egist er . Cou n t er oper a t ion m ode. E dge eva lu a t ion select ion : sin gle/dou ble/qu a d (on ly for ph a se-sh ift ed sign a l in pu t ) Cou n t dir ect ion select ion . Cou n t er clea r con t r ol:syn ch r on ou s/ a syn ch r on ou s clea r . F ixed/va r ia ble edge clea r . 8 bit da t a bu s. Low power CMOS t ech n ology. TTL com pa t ible. Sin gle 5V power su pply. 28 pin DIP .
2, Typical Applications N C m a ch in e t ools P r ecision posit ion er s Robot a r m con t r oller s Speed con t r oller s for r ot a t in g m a ch in es E lect r on ic ga u ges F r equ en cy cou n t er s
Pin configuration (Top view)
VSS CLK RESET CE C/D RD WR LD LT D0 D1 D2 D3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD INT EQ UD/AB DIR VSS A/UP B/DN Z/CLR D7 D6 D5 D4 VDD
ZEN2 0 0 2 AP
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ZEN2002AP
3, Block Diagram
CE C/D RD WR LT LD
Control logic
Command register (8bit)
Status register (8bit)
Reference register (24bit) Interrupt control logic Comparator (24bit) INT
EQ
Latch register (24bit)
UD/AB DIR A/UP B/DN Z/CLR Phase discrimination
Up/down counter (24bit)
UP PULSE DOWN PULSE COUNTER CLEAR
RESET CLK VDD VSS
Preload register (24bit)
D7~ D0
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4, Block function 1) Up/down counter It is presettable up/down binary counter of 24 bit length. The count value can be read out from the latch register via the data bus without influencing to the count operation. The counter value is initialized by loading the preload register(24bits) or via the data bus every 8 bits. 2) Reference register It is a writing register of 24 bit length. The written data is compared by the comparator with the count value of the up/down counter. 3) Comparator It is a digital comparator of 24 bit length. The data of the reference register is always compared with the counter value of the up/down counter and the result is output to EQ(26Pin), the status register, and the interruption control logic. 4) Preload register It is a data register of 24 bit length. Its data is loaded into the up/down counter by the external signal LD(8Pin) or the command(load instruction). 5) Latch register It is a data register only for reading 24 bit length. It latch the count value of the up/down counter by the external signal LT(9Pin) or the command(latch instruction). 6) Command register It is a register for the command writing. ( 8 bits ) The controls of loading instruction, latch instruction, count clear control, and register (byte) selection and count mode changes, etc. are done by using this register. 7) Status register It is a register for the status reading. ( 8 bits ) It monitors the state of abnormal input detection, the state of input signal(A,B,Z), the state of the latch register, count direction, the state of coincidence detection(count value = preset value), and the state of interruption output (INT). 8) Phase distcrimination logic The count pulse for the up/down counter is generated from the input signal of A/UP(22Pin) and B/DN(21Pin). 9) Control logic The read/write timing control, the decoding about the command data, and the status flag control.
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5, Pin Description Pin No. 2 3 Signal CLK RESET I/O I I Function System clock System reset Up/down counter, phase discrimination logic, command register and the status register are initialized. Chip enable Command/data select "High":command/status "Low":data Read strobing Write strobing Data loading The data of the preload register is loaded to the up/down counter Count data latch The count value of the up/down counter is latched to the latch register. Data bus Bidirectional data bus ( 8 bits ). It is used to transmit and receive the command, status and data.
4 5 6 7 8 9 10 11 12 13 16 17 18 19 20 21 22 24 25 26 27
CE C/D RD WR LD LT D0 D1 D2 D3 D4 D5 D6 D7 Z/CLR B/DN A/UP DIR UD/AB EQ INT
I I I I I I I/O
I I I I I O O
1 15
VSS VDD
Counter clear Count pulse input B Count pulse input A Count direction selection Input signal selection Selection up/down or phase-shifted pulse Coincidence detection output Coincidence detection output of count value and preset value of reference register. Interruption output When the coincidence of the count value and the preset value is detected, it outputs. It maintains to reset or the reset command execution. Power supply ( 5v ) Ground ( 0v )
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6, Basic operation The read/write operation is selected according to CE, C/D, RD, and WR. CE H L L L L C/D L L H H RD L H L H WR H L H L Operation Disable The data reading The data writing Status reading Command writing
1) Selection of count pulse input UD/AB H L Input pulse signal Up/down pulse Phase-shifted pulse A/UP Up pulse Phase-A pulse B/DN Down pulse Phase-B pulse
2) Access pointer The internal register is selected by setting the access pointer of the command register. Once setting the pointer, it is incremented automatically after reading or writing 1 byte data. ( automatical increment function ) 3) Abnormal input detection The function is to check whether it is normal state transition () when the phase-shifted pulse is input. When the abnormal state transition happens , D7 of the status register becomes "H". AB 01 00 AB 11 10 : noamal transition : abnormal transition Example of causing abnormal a. When it is not possible to sample signal accurately because the pulse input frequency exceeded 1/4 of the system clock frequency. b. When you pick up noise.
4) Selection of count edge ( C = count , nc = no count ) Up/down pulse input UP DN Single C C C C nc
Phase-shifted pulse input ( CW (phase-A preceding)) A B Single Double Quad C C C nc nc nc nc C nc CCC
( CCW (phase-B preceding)) A B Single Double Quad nc nc nc C CC nc nc C C C C ZENIC Inc.
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7, Command register D7 D6 D5 D4 D3 D2 D1 D0 | | (command ID) 0 0 = Load/latch and register selection 0 1 = Phase-Z input control 1 0 = Edge evaluation and clearness timing control 1 1 = Interruption output control (1) Latch and loading/register selection D7 D6 D5 D4 D3 D2 D1 D0 0 0 LD LT RS1 RS0 BS1 BS0 | | | | 0 0 -- Lower 8 bits. (D) ( the pointer is automatically incremented ) | | | | 0 1 -- Middle 8 bits. | | | | 1 0 -- Upper 8 bits. | | 0 0 --------------- Up/down counter (D) ( the pointer is automatically incremented ) | | 0 1 --------------- Comparison register | | 1 - ---------------- Preload register | 1 ------------------------ The data latch instruction 1 ---------------------------------- The data loading instruction (2) Phase-Z input control D7 D6 D5 D4 D3 D2 D1 D0 01 00- ZE1 ZE0 0 0 -0 1 -1 0 -1 1 -(3) Edge evaluation and clear timing D7 D6 D5 D4 D3 D2 D1 D0 10 0 0 SYNC ZC MS1 MS0 | | 0 0 -| | 0 1 -| | 1 - -| 0 ------------| 1 ------------0 ------------------1 -------------------
No operation Phase-Z input invalidity (D) Limiting phase-Z input next effective Every time, phase-Z input is effective.
Single Double Quad (D) A changeable edge is clear. A fixed edge is clear (D). Asynchronous clearness (D) Synchronous clearness
(4) Interruption output control D7 D6 D5 D4 D3 D2 D1 D0 110 0- INT 0 ---- Interruption output disable (D) 1 ---- Interruption output enable
(D): Default
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8 , Status register D7 D6 D5 D4 D3 D2 D1 D0 AI Z A B DTR U/D EQ INT | | | | | | | 0 ------| | | | | | | 1 ------| | | | | | 0 ------------| | | | | | 1 ------------| | | | | 0 ------------------| | | | | 1 ------------------| | | | 0 -------------------------| | | | 1 -------------------------| | | 0 -------------------------------| | | 1 -------------------------------| | 0 --------------------------------------| | 1 --------------------------------------| 0 -------------------------------------------| 1 -------------------------------------------0 -------------------------------------------------1 --------------------------------------------------
INT = "L" " = "H" Count value = preset value " 1" Down count Up count Latch register Not ready " Data ready B/DN = "L" = "H" A/UP = "L" = "H" Z/CLR = "L" = "H" Abnormal input undetection " detection
AI is reset after the status reading and DTR is after reading the data of one byte in "0". 9 , Operation timing (1) Count operation Phase-shifted pulse input CLK A/UP B/DN Counter Single Double Quad
N N N N+1
N+1 N+2 N+1
N N N
N+1 N+2 N+3 N+4 N+3 N+2 N+1
Up/down pulse input CLK A/UP B/DN Counter N N+1 N
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(2) Clear operation Synchronous clear ( Only phase-shifted pulse input ). direction CW (phase-A preceding) direction CCW (phase-B preceding) CLK A/UP B/DN Z/CLR Counter operation 0000H Asynchronous clear Variable edge direction CW (phase-A preceding) CLK Z/CLR Counter operation 0000H Fixed edge CLK Z/CLR Counter operation 0000H (3) The data loading and latch operation timing CLK LD LT Counter Latch register L N M(When the value of preload register is M) M start start operation 0000H start start operation 0000H start
direction CCW (phase-B preceding)
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10, Electric characteristic 1) Absolute maximum ratings ( VSS = 0v ) Item Sign Values Supply voltage VDD -0.3 ~ 7.0 Input voltage VI VSS-0.3 ~ VDD+0.3 Output voltage VO VSS-0.3 ~ VDD+0.3 Peak output current IOL +40 IOH -20 Permissible loss PT 495 Operation temperature Topr 0 ~ 70 Reservation temperature Tstg -55 ~ 150 2) Recommended operating conditions ( VSS = 0v ) Item Sign Min. Typical Supply voltage VDD 4.75 5.00 Operation temperature Ta 0 3) I/O capacity ( VDD=V1=0v f=1MHz Ta=25 C ) Item Sign Min. Typical Max. Input terminal CIN 10 20 Output terminal COUT 10 20 I/O terminal CI/O 10 20
Unit V V V mA mA mW C C
Max. 5.25 70
Unit V C
Unit pF pF pF
4) DC characteristics ( at the recommended operating conditions ) Item Sign conditions Standby current IDDS VI=VDD or VSS Operation current IDDO VI=VDD or VSS f=20MHz Output open Input H level VIH (group A,D,E) voltage L level VIL (group A,D,E) Input leakage ILI VI=VDD or VSS (group A,B) current IPLPU VI=VDD (group E) Input threthold VT+T4 VDD=5.0V (group B) VT-T4 Hysteresis width Vtt4 VDD=5.0V (group B) Output H level VOH IO=-1.6mA V I=VDD or VSS (group D,F) voltage L level VOL IO=12mA VI=VDD or VSS (group C) IO=4mA VI=VDD or VSS (group D,F) Output leakage IOZ VO=HI-Z VI=VDD or VSS VO=VDD current (group C) VO=HI-Z VI=VDD or VSS VO=VDD or VSS (group D) Pullup register RPU1 VI=0.0V VDD=5.0V (group E) group group group group group group A:CE,C/D,RD,WR,CLK,RESET B:LT,LD,Z/CLR,B/DN,A/UP C:INT D:D0,D1,D2,D3,D4,D5,D6,D7 E:DIR,UD/AB F:EQ
Min.
Typical
2 0 -10 -20 0.6 0.2 VDD - 0.6 1.7 1.2 0.5
Max. Unit 100 A 30 mA VDD V 0.8 V 10 A 20 A 2.4 V V V V 0.4 0.4 10 10 V V A A K
-10 -10 12 30
75
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11 , AC characteristics ( Ta=0-70 C Vcc=5v }5% ) Item C/D,CE setup time(D7-D0) C/D,CE hold time(D7-D0) Data setup time (WR-) Data hold time (WR-) WR pulse width C/D,CE setup time (RD ) C/D,CE hold time (RD-) RD pulse width Data access time (RD ) Data float delay time(RD- ) Clock H/L pulse width Clock rise up time Clock fall down time Clock cycle time Reset pulse width LD pulse width LT pulse width CLK--EQ delay time CLK--EQ-delay time A,B high level width A,B low level width A,B phase difference time Z high level width Z pulse width UP high level time UP low level time DN high level time DN low level time UP- -DN- set time CLK--INT delay time Sign tAW tWA tDW tWD tWW tAR tRA tRR tRD tDF r f cy tRST tLDW tLDW tEQF tEQR tPWABH tPWABL tSAB tSZ tZZ tUPH tUPL tDNH tDNL tUDS tINTF Condition Min 0 0 25 10 50 50 30 50 Max Unit nS nS nS nS nS nS nS nS 50 nS 20 nS nS 3 nS 3 nS nS nS nS nS 20 nS 20 nS nS nS nS nS nS nS nS nS nS nS 121 nS
22
50 cy 2+50 50 50
Synchronous clear Asynchronous clear Up/down mode " " " " load capacity 75pF
cy 2+20 cy 2+20 cy+10 cy 2+20 cy+20 cy+20 cy+20 cy+20 cy+20 0
Write cycle C/D,CE C/D:"High" Command writing "Low" Data writing tAW WR tWW tDW tWD tWA
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ZEN2002AP
Read cycle C/D,CE C/D:"High" Status reading "Low" Data reading RD
tAR D7~D0 tRD
tRR
tRA
tDF
Clock waveform
CLK r f cy
Reset waveform RESET tRST
LD (LT) tLDW (tLTW)
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ZEN2002AP
Phase-shifted pulse input tPWABH A/UP tSAB tSAB tSAB tSAB tPWABL
B/DN tPWABH tPWABL
Z/CLR (Synchronous clear)
tSZ
tSZ
Z/CLR (Asynchronous clear)
tZZ
Up/down pulse input A/UP tUPL tDNH B/DN tDNL tUPH
Output timing of EQ,INT signal CLK UDC:count value of up/down counter UDC EQ tEQF INT tINTF tEQR (SP-1) (SP) (SP+1) (SP+2) (SP):set value of reference register
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12, Application note Z80
8086
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13, Package Outlines( dimensions in mm )
1
28
37. 0 } 0. 5
14
15 1. 0t y p. 3. 3 } 0. 1 13. 0 } 0. 2 3. 3 } 0. 3
0. 25+0. 2 0 ` 15 K
15. 24 } 0. 5
2. 54 } 0. 25.
0. 5 } 0. 1
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ZENIC r eser ves t h e r igh t t o m a ke ch a n ges in it s pr odu ct wit h ou t a n y n ot ice t o im pr ove r elia bilit y, fu n ct ion or design . ZENIC does n ot a ssu m e a n y lia bilit y a r isin g ou t of t h e a pplica t ion or u se of a n y pr odu ct or cir cu it descr ibed h er ein ;n eit h er does it con vey a n y licen se u n der it s pa t en t r igh t s n or t h e r igh t s of ot h er s. In for m a t ion con t a in ed in t h is pu blica t ion r ega r din g device a pplica t ion s a n d t h e lik e is in t en ded t h r ou gh su ggest ion on ly a n d m a y be su per seded by u pda t es. ZENIC pr odu ct s a r e n ot design ed, in t en ded, or a u t h r ized for u se a s com pon en t s in syst em s in t en ded for su r gica l im pla n t in t o t h e body, or ot h er a pplica t ion s in t en ded t o su ppor t or su st a in life, or for a n y ot h er a pplica t ion in wh ich t h e fa ilu r e of t h e ZE N IC pr odu ct s cou ld cr ea t e a sit u a t ion wh er e per son a l in ju r y or dea t h m a y occu r . Z80 is a r egist er ed t r a dem a r k of Zilog Inc. 6809 is a r egist er ed t r a dem a r k of Motorola Inc. 8086 is a r egist er ed t r a dem a r k of Intel Corp. All r igh t r eser ved. Copyr igh t 1991, ZENIC INC.
ZENIC Inc.
U RL h t t p://www.zen ic.co.jp/ 1-17-14, Oh ga ya Oh t su Sh iga 520-2144, J AP AN F a x. +81-77-543-9431 E -m a il su ppor t @zen ic.co.jp ZENIC Inc.
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